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amd64_edac: Fix logic to determine channel for F15 M30h processors
authorAravind Gopalakrishnan <Aravind.Gopalakrishnan@amd.com>
Tue, 21 Jan 2014 21:03:36 +0000 (15:03 -0600)
committerBorislav Petkov <bp@suse.de>
Fri, 7 Feb 2014 14:01:19 +0000 (15:01 +0100)
commit191cdfa4749f57be555850e36eed2b27afc5f9ca
tree39d2915d2874c3ea9494909288943b193d4c209btree | snapshot
parente791cfbd99c431de2efafe669002068ff9021ad9commit | diff
amd64_edac: Fix logic to determine channel for F15 M30h processors

Update current channel selection logic to include F15h, M30h memory
controllers.

Refer F15 M30h BKDG D18F2x110[7:6] (DRAM Controller Select Low)
(Link:http://support.amd.com/TechDocs/49125_15h_Models_30h-3Fh_BKDG.pdf)

Signed-off-by: Aravind Gopalakrishnan <Aravind.Gopalakrishnan@amd.com>
Link: http://lkml.kernel.org/r/1390338216-3873-1-git-send-email-Aravind.Gopalakrishnan@amd.com
Signed-off-by: Borislav Petkov <bp@suse.de>
drivers/edac/amd64_edac.c diff | blob | history
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