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(parent: 1631f9c) | patch
fix(gpt): correct the GPC enable sequence
authorKathleen Capella <kathleen.capella@arm.com>
Fri, 22 Jul 2022 20:26:36 +0000 (16:26 -0400)
committerKathleen Capella <kathleen.capella@arm.com>
Thu, 25 Aug 2022 04:22:01 +0000 (00:22 -0400)
commit14cddd7a58799c8a9d349a4adc0136c1ab5d0b6c
tree7047669b70d067ad7fb018123f26ec4f065173b7tree | snapshot
parent1631f9c75c6e9667a320c8daf6a05bb49b80826ecommit | diff
fix(gpt): correct the GPC enable sequence

Since GPC control register fields are permitted to be cached in a TLB,
invalidate TLB after setting fields to ensure future checks are using
the updated values.

Signed-off-by: Kathleen Capella <kathleen.capella@arm.com>
Change-Id: I95630b40b673363bbf74da2705deca03089fff3a
lib/gpt_rme/gpt_rme.c diff | blob | history
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