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(parent: 8c68d39) | patch
riscv: starfive: Add SYS_CACHE_SHIFT_6 to enable SYS_CACHELINE_SIZE
authorMinda Chen <minda.chen@starfivetech.com>
Mon, 7 Aug 2023 08:53:37 +0000 (16:53 +0800)
committerLeo Yu-Chi Liang <ycliang@andestech.com>
Thu, 10 Aug 2023 02:58:01 +0000 (10:58 +0800)
commit12ba87fe50c05502606c9011e4f7e15033ab0edd
tree3fdc400dbe79d3b191e56eaa1ee20d9676157668tree | snapshot
parent8c68d399dba5d22ca0f21c47a2d8c81dac277fb2commit | diff
riscv: starfive: Add SYS_CACHE_SHIFT_6 to enable SYS_CACHELINE_SIZE

Some device driver need SYS_CACHELINE_SIZE macro. Add StarFive
SYS_CACHE_SHIFT_6 to enable it.

Signed-off-by: Minda Chen <minda.chen@starfivetech.com>
Reviewed-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
arch/riscv/cpu/jh7110/Kconfig diff | blob | history
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