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(parent: 5916afd) | patch
drm/i915/gt: Only wait for register chipset flush if active
authorChris Wilson <chris@chris-wilson.co.uk>
Mon, 18 Nov 2019 18:49:33 +0000 (18:49 +0000)
committerChris Wilson <chris@chris-wilson.co.uk>
Tue, 19 Nov 2019 10:11:29 +0000 (10:11 +0000)
commit11069c7283d04825c33bd3d1a3acbb70ed093eaf
treed629bfa2285133c24ab29e6c81ae43e5a6f1a5f3tree | snapshot
parent5916afd63adc279b4c2f228a63da9dcbb1597676commit | diff
drm/i915/gt: Only wait for register chipset flush if active

Only serialise with the chipset using an mmio if the chipset is
currently active. We expect that any writes into the chipset range will
simply be forgotten until it wakes up.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20191118184943.2593048-8-chris@chris-wilson.co.uk
drivers/gpu/drm/i915/gt/intel_gt.c diff | blob | history
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