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(parent: b98decc) | patch
drm/amdgpu/gfx10: update CGTS_TCC_DISABLE and CGTS_USER_TCC_DISABLE register offsets...
authorchen gong <curry.gong@amd.com>
Fri, 29 Jan 2021 07:37:45 +0000 (15:37 +0800)
committerAlex Deucher <alexander.deucher@amd.com>
Tue, 2 Feb 2021 22:34:56 +0000 (17:34 -0500)
commit10abd88742889b612adf5cb410250bd3cba16ca4
tree7856b5ca21cf47029bfbaf4b186b820838d3683ctree | snapshot
parentb98decc49f13d9ab0c13b9c7281e6eca9262040bcommit | diff
drm/amdgpu/gfx10: update CGTS_TCC_DISABLE and CGTS_USER_TCC_DISABLE register offsets for VGH

For Vangogh:
The offset of the CGTS_TCC_DISABLE is 0x5006 by calculation.
The offset of the CGTS_USER_TCC_DISABLE is 0x5007 by calculation.

Signed-off-by: chen gong <curry.gong@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c diff | blob | history
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