clk: sunxi-ng: sun8i-a23: Set CLK_SET_RATE_PARENT for audio module clocks

clk: sunxi-ng: sun8i-a23: Set CLK_SET_RATE_PARENT for audio module clocks

The audio module clocks are supposed to be set according to the sample
rate of the audio stream. The audio PLL provides the clock signal for
these module clocks, and only it is freely tunable.

Set CLK_SET_RATE_PARENT for the audio module clocks so their users can
properly tune the clock rate.

Fixes: 48fb9bf7eb63 ("clk: sunxi-ng: Add A23 CCU")
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>