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clk: renesas: r9a07g044: Add SDHI clock and reset entries
authorBiju Das <biju.das.jz@bp.renesas.com>
Thu, 7 Oct 2021 11:14:34 +0000 (12:14 +0100)
committerGeert Uytterhoeven <geert+renesas@glider.be>
Fri, 8 Oct 2021 13:10:36 +0000 (15:10 +0200)
commit0fb343c2ba1fde8c0fd9b20a2423999701f75c19
treeee3fae4574573a3b47c47aafd688ea8230c5d709tree | snapshot
parenta7805d1e1d640887a5585ccb0dd375f8729aa34bcommit | diff
clk: renesas: r9a07g044: Add SDHI clock and reset entries

Add SDHI{0,1} mux, clock and reset entries to CPG driver.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/20211007111434.8665-3-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
drivers/clk/renesas/r9a07g044-cpg.c diff | blob | history
drivers/clk/renesas/rzg2l-cpg.h diff | blob | history
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