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(parent: 0a55b51) | patch
drm/i915/tgl/dsi: Set latency PCS_DW1 for tgl
authorVandita Kulkarni <vandita.kulkarni@intel.com>
Tue, 30 Jul 2019 07:36:44 +0000 (13:06 +0530)
committerUma Shankar <uma.shankar@intel.com>
Thu, 8 Aug 2019 13:07:50 +0000 (18:37 +0530)
commit0f631347c1151752960839bbdf947968c045cfd5
tree28f137ad7831543a8f462fd042bf3cb73f3ecb6dtree | snapshot
parent0a55b51491a5879dbfb67d4939f5b6e880384309commit | diff
drm/i915/tgl/dsi: Set latency PCS_DW1 for tgl

Latency programming remains same as that of ICL and
setting latency otimization for PCS_DW1 lanes is same as
that of EHL, hence extending it to TGL.

Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
Reviewed-by: Uma Shankar <uma.shankar@intel.com>
Signed-off-by: Uma Shankar <uma.shankar@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190730073648.5157-3-vandita.kulkarni@intel.com
drivers/gpu/drm/i915/display/icl_dsi.c diff | blob | history
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