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ARC: HSDK: CGU: Update AXI, TUN, ARC clock options
authorEugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Tue, 16 Jan 2018 17:44:25 +0000 (20:44 +0300)
committerAlexey Brodkin <abrodkin@synopsys.com>
Fri, 19 Jan 2018 14:59:35 +0000 (17:59 +0300)
commit0f4b99d0693fa8e61ee4732195b5df8877c476cb
tree7d10db927078e61b2b4b718ee18cdbc521b73e66tree | snapshot
parent7e01d80538820df43d338403143e7b9271162c73commit | diff
ARC: HSDK: CGU: Update AXI, TUN, ARC clock options

Update default AXI, TUN, ARC clock set options:
instead of changing only IDIV divider settings adjust also domain PLL
settings.

Add support of TUN_ROM and TUN_PWM clocks (subclocks of TUNN_PLL)

Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
drivers/clk/clk-hsdk-cgu.c diff | blob | history
include/dt-bindings/clock/snps,hsdk-cgu.h diff | blob | history
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