]> git.baikalelectronics.ru Git - arm-tf.git/commit
Workaround for Neoverse N1 erratum 1800710
authorjohpow01 <john.powell@arm.com>
Tue, 2 Jun 2020 18:14:11 +0000 (13:14 -0500)
committerJohn Powell <john.powell@arm.com>
Thu, 25 Jun 2020 19:58:35 +0000 (19:58 +0000)
commit0e0521bdfce73be7dbded23e560b3dab1ff1af2d
treecd1fba5d1538fae0b9d808bd9244d7d9e661fc44
parent24cdbb22a9da2eb7d07592774777012552a5dd41
Workaround for Neoverse N1 erratum 1800710

Neoverse N1 erratum 1800710 is a Cat B erratum, present in older
revisions of the Neoverse N1 processor core.  The workaround is to
set a bit in the ECTLR_EL1 system register, which disables allocation
of splintered pages in the L2 TLB.

This errata is explained in this SDEN:
https://static.docs.arm.com/sden885747/f/Arm_Neoverse_N1_MP050_Software_Developer_Errata_Notice_v21.pdf

Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: Ie5b15c8bc3235e474a06a57c3ec70684361857a6
docs/design/cpu-specific-build-macros.rst
include/lib/cpus/aarch64/neoverse_n1.h
lib/cpus/aarch64/neoverse_n1.S
lib/cpus/cpu-ops.mk