]> git.baikalelectronics.ru Git - kernel.git/commit
LoongArch: Refactor cache probe and flush methods
authorHuacai Chen <chenhuacai@loongson.cn>
Wed, 12 Oct 2022 08:36:14 +0000 (16:36 +0800)
committerHuacai Chen <chenhuacai@loongson.cn>
Wed, 12 Oct 2022 08:36:14 +0000 (16:36 +0800)
commit0d027d7d3d08e1491a8004d25ac0c1ad313bea64
tree414693038d707d37b34edfee4f4ece650275996a
parent6672fb5c900ca098a0b0f0b1f9b3ae733714eaf2
LoongArch: Refactor cache probe and flush methods

Current cache probe and flush methods have some drawbacks:
1, Assume there are 3 cache levels and only 3 levels;
2, Assume L1 = I + D, L2 = V, L3 = S, V is exclusive, S is inclusive.

However, the fact is I + D, I + D + V, I + D + S and I + D + V + S are
all valid. So, refactor the cache probe and flush methods to adapt more
types of cache hierarchy.

Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>
arch/loongarch/include/asm/cacheflush.h
arch/loongarch/include/asm/cacheops.h
arch/loongarch/include/asm/cpu-features.h
arch/loongarch/include/asm/cpu-info.h
arch/loongarch/include/asm/loongarch.h
arch/loongarch/include/asm/setup.h
arch/loongarch/kernel/cacheinfo.c
arch/loongarch/kernel/traps.c
arch/loongarch/mm/cache.c
arch/loongarch/pci/pci.c