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(parent: edb9152) | patch
drm/msm/dsi: Updata LNn_CFG4 register settings for 28nm PHY
authorHai Li <hali@codeaurora.org>
Fri, 11 Sep 2015 19:56:09 +0000 (15:56 -0400)
committerRob Clark <robdclark@gmail.com>
Thu, 22 Oct 2015 19:39:54 +0000 (15:39 -0400)
commit0b2a93ab91597a2fa537e0be0b79c3302295f60b
tree0d86b5bf966f9e6d3a5ea9ea614c3bc6e6b7abectree | snapshot
parentedb91528eb7ec46d376d2e505ffb26062f55fe76commit | diff
drm/msm/dsi: Updata LNn_CFG4 register settings for 28nm PHY

The current settings for 28nm PHY data lane CFG4 registers do
not work with certain panels. This change is to modify them to
hw recommended values.

Signed-off-by: Hai Li <hali@codeaurora.org>
Signed-off-by: Rob Clark <robdclark@gmail.com>
drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c diff | blob | history
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