]> git.baikalelectronics.ru Git - kernel.git/commit
drm: Restore double clflush on the last partial cacheline
authorChris Wilson <chris@chris-wilson.co.uk>
Thu, 7 Jul 2016 08:41:12 +0000 (09:41 +0100)
committerDaniel Vetter <daniel.vetter@ffwll.ch>
Tue, 12 Jul 2016 13:57:13 +0000 (15:57 +0200)
commit04cdc366bae1aaa336e777c2fdc19efda061fcd6
tree170144da0a320697bc6df43b8a2062b377efb353
parent058e96b903db5a6366357796aa2d99553529b200
drm: Restore double clflush on the last partial cacheline

This effectively reverts

commit 63a0a43b84ac7020cbe10d74479e9fe962e84cc2
Author: Chris Wilson <chris@chris-wilson.co.uk>
Date:   Wed Jun 10 15:58:01 2015 +0100

    drm: Avoid the double clflush on the last cache line in drm_clflush_virt_range()

as we have observed issues with serialisation of the clflush operations
on Baytrail+ Atoms with partial updates. Applying the double flush on the
last cacheline forces that clflush to be ordered with respect to the
previous clflush, and the mfence then protects against prefetches crossing
the clflush boundary.

The same issue can be demonstrated in userspace with igt/gem_exec_flush.

Fixes: 63a0a43b84ac7 (drm: Avoid the double clflush on the last cache...)
Testcase: igt/gem_concurrent_blit
Testcase: igt/gem_partial_pread_pwrite
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=92845
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: dri-devel@lists.freedesktop.org
Cc: Akash Goel <akash.goel@intel.com>
Cc: Imre Deak <imre.deak@intel.com>
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
Cc: Jason Ekstrand <jason.ekstrand@intel.com>
Cc: stable@vger.kernel.org
Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Link: http://patchwork.freedesktop.org/patch/msgid/1467880930-23082-6-git-send-email-chris@chris-wilson.co.uk
drivers/gpu/drm/drm_cache.c