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(parent: 66cf68a) | patch
drm/amdgpu: Clear vce&uvd ring wptr for SRIOV
authorFrank Min <Frank.Min@amd.com>
Mon, 12 Jun 2017 02:53:19 +0000 (10:53 +0800)
committerAlex Deucher <alexander.deucher@amd.com>
Tue, 15 Aug 2017 18:45:45 +0000 (14:45 -0400)
commit03d6c9d475840598bf4486e0906d41f41bb26654
tree53fcd7b4af73546813cba7efdce01371b4647f52tree | snapshot
parent66cf68a50b60c38526db0266ba2eb8dc60fe41d2commit | diff
drm/amdgpu: Clear vce&uvd ring wptr for SRIOV

MMSCH FW need to get the wptr from 0 after it get the mailbox request
from driver, since every time kick the mailbox, mmsch thinks that it
is the first time engine start to initialize.

Signed-off-by: Frank Min <Frank.Min@amd.com>
Signed-off-by: Xiangliang.Yu <Xiangliang.Yu@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c diff | blob | history
drivers/gpu/drm/amd/amdgpu/vce_v4_0.c diff | blob | history
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