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(merge: 87a9595 aacec25)
Merge tag 'xilinx-for-v2020.04-rc4' of https://gitlab.denx.de/u-boot/custodians/u...
authorTom Rini <trini@konsulko.com>
Mon, 2 Mar 2020 14:20:12 +0000 (09:20 -0500)
committerTom Rini <trini@konsulko.com>
Mon, 2 Mar 2020 14:20:12 +0000 (09:20 -0500)
commit02c782450e748dd0e98390cb247bf2a017bd9244
tree4e30bec98504a3923d40df2594b48c173032e192tree | snapshot
parent87a9595a55af0769c7e8d4836f96a29bbe2f9edecommit | diff
parentaacec25f52b642cd83bd2f0b6cdb2180ba8357c5commit | diff
Merge tag 'xilinx-for-v2020.04-rc4' of https://gitlab.denx.de/u-boot/custodians/u-boot-microblaze

Xilinx fixes for v2020.04-rc4

- Fix link good bit handling in dp83867
- Rename generic Zynq defconfig
- Fix zybo z7 low leve setup
- Fix error path in zynq_gem driver and fix 64bit usage
- Fix invalid clock name quieries for Versal
- Fix zynq/zynqmp SPL low level configuration via DT selection
"Das U-Boot" Source Tree.