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drm/tegra: hdmi: Registers are 32-bit
authorThierry Reding <treding@nvidia.com>
Mon, 8 Dec 2014 15:25:14 +0000 (16:25 +0100)
committerThierry Reding <treding@nvidia.com>
Tue, 27 Jan 2015 09:14:37 +0000 (10:14 +0100)
commit01a2ca51ac70efad2c69c47ed61d307433da7c54
treeccda1ff7b189afc970bce971a3e53651f2013281tree | snapshot
parent0b6af63493a78b504c62ffb8d55ac2425c73d5b3commit | diff
drm/tegra: hdmi: Registers are 32-bit

Use a sized unsigned 32-bit data type (u32) to store register contents.
The HDMI registers are 32 bits wide irrespective of the architecture's
data width.

Signed-off-by: Thierry Reding <treding@nvidia.com>
drivers/gpu/drm/tegra/hdmi.c diff | blob | history
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