clk: tegra: Add sor_safe clock

clk: tegra: Add sor_safe clock

The sor_safe clock is a fixed factor (1:17) clock derived from pll_p. It
has a gate bit in the peripheral clock registers. While the SOR is being
powered up, sor_safe can be used as the source until the SOR brick can
generate its own clock.

Signed-off-by: Thierry Reding <treding@nvidia.com>